Aspects of the present invention relate generally to the field of integrated circuit design, and in particular to techniques for verification and debug of such designs.
Hardware designers, for example integrated circuit (IC) designers, do not always design every component of a new hardware device. While designers may design one or more components of a particular device, they often employ component designs (also known as intellectual property, or design IP) from one or more third-party providers. Using components from third-party providers can facilitate the design by avoiding the need for the designer to design every aspect of the device's functionality. The design IP implemented in a device typically provide operations consistent with a standard protocol or with a proprietary protocol of the design IP provider.
Multiple aspects of a design typically may be tested. For example, a hardware design may undergo architectural simulation and analysis and debugging where the functionality of each component being implemented in the design is tested, for example, with transaction level modeling (TLM) or bus functional modeling. The hardware design may additionally undergo circuit simulation and analysis where the signals between components are tested, for example using register transition level (RTL) analysis. Other steps may include: design simulation, for example to model the components of a design together; design and software emulation, for example to model execution of software elements executing on a modeled design; FPGA prototyping; hardware and software co-verification; and post-silicon validation.
Each of these testing stages typically utilizes different verification platforms and/or different interface and driver tools, therefore limiting the reuse of verification methods, and tools relevant to verification. For example, hardware designers may employ a hardware based verification platform to perform certain tests on a completed design. Hardware verification platforms typically enable testing of the various components of the design which facilitates design analysis and debugging operations to identify and fix defects that are encountered. Such testing may require the creation of device specific drivers to verify that the inputs and outputs over a communication medium conform to a standard or predefined protocol. These drivers, sometimes referred to as firmware, are software stacks created to manage the design IP.
However, driver development is error-prone and time consuming. Conventionally, the drivers and tools necessary to test the design IP of a device are not implemented until after the design IP has been completed and further may require rewrites whenever a design IP is changed. Where the design IP is only a partial implementation of the protocol, the driver for the design IP will be incomplete. In such cases, the reuse of the driver for the next revision of the design IP becomes difficult. Because the driver is often developed based on the completion of the design IP, the testing process is significantly delayed because it is not parallelized with the design IP development. Additionally, the driver interface between an operating system and a device under test are often provided to the designer by the design IP developer in the context of a specific operating system information that is often proprietary, incomplete or ambiguous. As a result, the operating system and the driver may not function correctly together. Additionally, it is difficult to test the developed driver under all operating conditions of the design. For example, it is not possible to create all the relevant conditions during driver validation and many device protocol related conditions are not handled in the driver. Currently, testing of design IP is executed with a limited software stack. For example, the bare-metal driver sequences are developed to provide only limited testing from a software perspective. Once the particular test is complete, these sequences are typically discarded.
Accordingly, the art requires a system to efficiently test design IP, the design that contain the design IP, and the related drivers before the design under test is available.